Download e-book for iPad: Advances in Computer Systems Architecture: 9th Asia-Pacific by James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)

By James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)

ISBN-10: 3540230033

ISBN-13: 9783540230038

ISBN-10: 354030102X

ISBN-13: 9783540301028

On behalf of this system committee, we have been happy to give this year’s application for ACSAC: Asia-Paci?c computers structure convention. Now in its 9th yr, ACSAC keeps to supply a good discussion board for researchers, educators and practitioners to return to the Asia-Paci?c area to replace principles at the most modern advancements in computers structure. This yr, the paper submission and evaluation tactics have been semiautomated utilizing the loose model of CyberChair. We acquired 152 submissions, the most important quantity ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee contributors for evaluate. all the papers have been reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the assessment approach. while reviewers claimed insufficient services, extra reviewers have been solicited. finally, we acquired a complete of 594 stories (3.9 in step with paper) from committee individuals in addition to 248 coreviewers whose names are stated within the court cases. we want to thank them all for his or her time and e?ort in supplying us with such well timed and fine quality reports, a few of them on super brief notice.

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Additional resources for Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings

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ACSAC 2004, LNCS 3189, pp. 16–29, 2004. © Springer-Verlag Berlin Heidelberg 2004 Efficient Victim Mechanism on Sector Cache Organization 17 tium® 41[5], SUN’s SPARC™[6] and IBM’s POWERPC™ G4™[7]/G5™[8] all employ sector cache in their cache organization. This work intends to propose and evaluate further optimization techniques to improve performance of a sector cache. One of those designs is the victim cache[9]. A victim cache includes an additional victim buffer. When a line is replaced it is put into this small buffer which is full associative instead of just being discarded.

Our concern about this design is that the additional tag storage, say N-l address tags and s-ratio * log2N selection tags for each line, need large amount of extra storage. Seznec himself use large(32 or 64) s-raio, which will make the validity check and coherence control very complex, to reduce tag storage before decoupling. We tried to implement this idea and saw the line-fill-in and line-replacement policy is important for the performance. If with a line-based-LRU-like fill-in/replacement policy proposed by ourselves, since Seznec did not give enough details of his policies, the decoupled sector cache will not perform better than our VST design, if with similar extra storage, given s-ratio range of 2~8.

We also propose and evaluate two different reliability enhancing schemes — RVC-P and RVC-C — that are proven to be quite useful. RVC-P is a much better alternative for ICR-P-PS where one may want simple parity protection. It can enhance reliability significantly by providing additional replicas in the replica victim cache without compromising performance. , BaseECC). RVC-C can increase the error detection/correction capability by comparing the primary data and the replica before the load returns.

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Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings by James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)

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